欢迎这样的你加入我们
1. 微电子、电子工程、计算机等相关专业学士以及以上学位
2. 对静态时序分析,综合,网表质量检查,形式验证,CDC,异步时序分析等的全部和部分有良好的了解,有相关工作经验。
3. 良好的团队合作精神和解决问题的能力
5. 掌握一定的脚本知识,如perl,python,tcl,csh等
6. P&R, ASIC design and DFT etc. knowledge is a plus.
Circuit Design Engineer (CAD)-上海
We are now looking for a CAD/Methodology Engineer for custom circuit design, to develop and maintain design methodologies, flows for high-performance low-power circuit design, contribute to NVIDIA's state-of-the-art products.
What you’ll be doing:
Develop design methodologies, tools, and flows for custom circuit design and verification
Support full custom design flow from schematic to GDSII
Internal CAD tool development, EDA tools integration, for simulation and physical verification
maintain custom circuit design environment and tools
What we need to see:
BS or above, major in EE/CS or equivalent experience
1+ years of practical experience
Good programming skills, experience in Perl/Shell/Tcl/Python is preferred
Good knowledge in deep submicron CMOS process and device
Familiar with circuit design tools and custom design flow
Experience in design/verification flow automation is a plus
Experience in physical verification tools like ICV/Calibre is a plus
Knowledge/experience in VXL/PCELL/CDF/SKILL language/netlisting/ is a plus
Must be a team player with effective written and verbal communication skills
Must be able to learn quickly and work independently
Layout Design Engineer
We are now looking for Mask Design Engineer for Digital IP team. The team develops the high performance digital IPs used in our chips. The main role is layout design for SRAM, ROM and STDcell using the most advanced IC process in the world.
What you’ll be doing:
Develop digital IP layouts with excellent PPA in the most advanced process node
Verify the layout in cell level and macro level
Maintain the layouts per requests from circuit designers or other internal customers
Create tools or scripts to improve work efficiency
What we need to see:
BS/MS in EE or equivalent experience
Fundamental knowledge in digital logic, semiconductor device and manufacturing process
Minimum 2 years working experience on digital or mixed-signal layout design
Familiar with Cadence design environment and ICV/Calibre verification tools
Excellent communication in English
DFT Engineer-上海
Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.
What you’ll be doing:
You'll be responsible for DFT verification environment setup, own DFT verification and bringup tasks for Clocks, Boundary Scan, Analog, MBIST, Scan, etc. You'll have chance to take the lead role for DFT verifications and bringup.
In long term, you can be a DFT lead for verification or extend the expertise to DFT design or methodology.
What we need to see:
• BSEE with 3+, MSEE with 2+ years of experience or PhD or equivalent working experinece in DFT or design verification.
• Good understanding on ASIC design and verification.
• Hands on experience on at least one DFT feature: Boundary Scan, 1500, MBIST, Scan, ATPG.
• Experience in silicon debug and bring-up on the ATE is a plus.
• Good exposure to clock design, timing/STA, place-n-route or power is a plus.
• Excellent analytical skills in verification and debug.
• Strong programming and scripting skills in Perl, Python or Tcl desired.
• Excellent written and oral communication skills in English with the curiosity to work on challenges.